Amplifiers are electronic devices that may be used to amplify signals, such as by increasing an amplitude of the signal, or to perform other processing of signals. Two example amplifiers include open-loop amplifiers and closed-loop amplifiers. One specific example of a closed-loop amplifier is a Class-D amplifier. FIG. 1 shows such an example closed-loop Class-D amplifier architecture according to the prior art. Closed-loop Class-D amplifier 100 includes a feed-forward path that includes an input gain block 122, a summer 102, a loop filter 104, a pulse-width-modulator (PWM) modulator 106, and a power stage block 108. Amplifier 100 also includes a feedback path 110 that starts at an output of the power stage block 108 and is coupled back to the summer 102. The output of the power stage block 108 can drive a speaker 112 or other transducer. Loop filter 104 may include a number of integrators, and the PWM generator 106 modulates the loop filter 104 output into a PWM signal.
Another example of an amplifier is an open-loop amplifier, which may be similar to the amplifier 100 of FIG. 1, but would not have the feedback path 110 and the loop filter 104 would instead be replaced with an analog filter. Closed-loop amplifiers may be preferred over open-loop amplifiers because closed-loop amplifiers can generally provide better total-harmonic distortion (THD) performance and have a better power supply rejection ratio (PSRR).
In either a closed-loop amplifier, such as shown in FIG. 1, or an open-loop amplifier (not shown), the loop filter 104 or the analog filter (not shown) has a direct-current (DC) offset VOS1 from the first integrator at the input of the loop filter 104 or input of the analog filter and a direct-current (DC) offset VOS2 from other downstream integrators that is reflected at the filter output. The DC offset may then be magnified by the PWM modulator/generator 106 and then applied directly to the speaker 112 with the fixed gain of PWM modulator/generator 106 during speaker power up and/or down when the closed-loop amplifier transitions from a closed-loop magnified state to a closed-loop steady state. “Closed-loop magnified state” refers to a state where the DC offset is magnified at the amplifier output without any loop filter attenuation. “Closed-loop steady state” refers to the state where the loop filter attenuates the offset VOS2 to almost zero and an amplifier output corresponds only to the DC offset VOS1. Depending upon the unity-gain-bandwidth of the loop filter 104, it may take many cycles before the magnified DC offset is suppressed. During the delay cycles, the magnified DC offset is not entirely suppressed, and an output of the amplifier may exhibit artifacts. When the amplifier is used to drive a speaker, such as in an audio amplifier, the speaker may create audible pop and/or click noises. Thus, there is a need to further reduce or eliminate the DC offsets VOS1 and VOS2.
In a conventional loop filter 104, or in an analog filter, the DC offset VOS1 is typically designed at a much lower level to reduce the pop noise, but DC offset VOS2 is not addressed because, in the closed-loop steady state operations, the contribution from DC offset VOS2 is attenuated by the first integrator and is almost zero.
One method of handling the DC offset and audible pops and clicks at an amplifier output is to use a dual-loop amplifier architecture. One example is provided in U.S. Pat. No. 8,686,789, which is incorporated by reference herein. FIG. 2 is a block diagram illustrating a dual-loop amplifier according to the prior art. The dual-loop amplifier 200 includes a primary loop 204 and a secondary loop 206. The dual-loop amplifier 200 receives analog input 250 through an input resistor RIN and provides an output signal 252 to drive speaker 202. The primary loop 204 includes a loop filter 208, a pulse-width-modulation (PWM) modulator/generator 210, a reference generator 212, and a power driver 214.
The reference generator 212 provides a reference signal 256, and the PWM modulator/generator 210 provides a corresponding modulated signal 258. The primary loop 204 further has a feedback resistor RFDBK coupled to an output of the power driver 214 and an input of the loop filter 208. The feedback resistor RFDBK, in conjunction with the input resistor RIN and/or programmable gain, determines a gain of the primary loop 204. The secondary loop 206 includes the loop filter 208, the PWM modulator/generator 210, the reference generator 212, and an auxiliary driver 216. Secondary loop 206 also includes auxiliary resistor RAUX. Auxiliary resistor RAUX is coupled between an output of the auxiliary driver 216 and an input of the loop filter 208. The auxiliary resistor RAUX, in conjunction with the input resistor RIN and the programmable gain, determines a gain of the secondary loop 206.
FIG. 3 shows an example fixed-gain PWM modulator/generator 300 in accordance with the prior art, which may be used, for example, as the PWM modulator/generator 106 of FIG. 1. PWM modulator/generator 300 includes fixed current sources 302 and 304, capacitor C, amplifier 306, and comparators 308 and 310. Current signals from current sources 302 and 304 provide one of the inputs to the PWM modulator/generator 300 at an inverting input of the amplifier 306, and the non-inverting input can be coupled to ground. The output of the amplifier 306 is a triangle or ramp reference signal Vramp, and the voltage signal Vramp is fed into each of the respective inverting inputs for the comparators 308 and 310. The loop filter outputs VsigP and VsigM are also fed into the corresponding comparators 308 and 310. The comparators 308 and 310 compare the loop filter outputs VsigP and VsigM and the reference voltage Vramp to produce digital PWM signals PWM_M and PWM_P.
FIG. 4 shows example signal timing diagrams and example relationships for the voltage inputs VsigP and VsigM and outputs PWM_P and PWM_M of comparators 308 and 310 for PWM modulator/generator 300 in FIG. 3 according to the prior art. For the diagram of FIG. 4, the PWM modulator/generator 300 is assumed to be configured in the closed-loop architecture shown in FIG. 1. The average voltage of modulator output PWM_Diff shown in line 402 is determined in accordance with the following equation:
            V      pwm_diff        =                  (                              V            sigP                    -                      V            sigM                          )            *                        V          DD                /                  (                                    I              C                        *            T                    )                      ,where T is ramp period or half of triangle period and VDD is the modulator supply voltage. The PWM modulator/generator gain is then defined by the following equation:
  gain  =                    V                  pwm          diff                                      V          sigP                -                  V          sigM                      =                  V        DD            /                        (                                    I              C                        *            T                    )                .            
The slope of the ramp reference signal Vramp shown as line 404 is fixed because the gain of the PWM generator 300 is fixed and does not vary. Because the slope of Vramp is fixed and the loop of the amplifier 100 of FIG. 1 has a limited bandwidth, during loop power up or down, any offset voltage or signal at the output of the loop filter 104 will be amplified through the feedforward path and outputted from the power stage block 108 when the loop filter 104 transitions from closed-loop magnified state to closed-loop steady state. This amplified offset can be heard through the speaker 112, such as in the form of an audible pop(s) or click(s).
Referring back to FIG. 4, the closed-loop amplifier is powered on at time t1 shown as time 412. Before being powered on, the loop filter differential output is zero, and PWM_Diff is zero. Between times t1 and t2 (shown as time 414), when the amplifier is in the closed-loop magnified state, the direct-current (DC) offset appears at loop filter outputs VsigP and VsigM and is amplified by the PWM generator to generate a non-zero PWM_Diff. After time t2, the loop filter starts to attenuate the offset. After time t3 at time 416, the loop filter runs in the closed-loop steady state, when the offset VOS2 is attenuated to a low level and only a small residual offset VOS1 remains in the PWM_Diff signal.
Shortcomings mentioned here are only representative and are included simply to highlight that a need exists for improved electrical components, particularly for amplifiers employed in consumer-level devices, such as mobile phones and media players. Embodiments described herein address certain shortcomings but not necessarily each and every one described here or known in the art.